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data book 1 3.00 hys 64/72v32300gu sdram-modules 3.3 v 32m 64/72-bit sdram modules 168-pin unbuffered dimm modules the hys 64v32300gu and hys 72v32300gu are industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 32m 64 and 32m 72 in 1 memory bank high speed memory arrays designed with 256m synchronous drams (sdrams) for non-parity and ecc applications. the dimms use -7.5 speed sorted 32m 8 sdram devices in tsop54 packages to meet the pc133 requirement and -8,-8a & -8b components for the standard pc100 applications. decoupling capacitors are mounted on the pc board. the pc board design is according to intels pc100 module specification. the dimms have a serial presence detect, implemented with a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168- pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25 (31.75 mm) height. ? 168 pin unbuffered 8 byte dual-in-line sdram modules for pc main memory applications ? pc100 and pc133 versions ? one bank 32m 64 and 32m 72 organisation ? optimized for byte-write non-parity or ecc applications ? fully pc board layout compatible to intels rev. 1.0 module specification ? programmed latencies: ? single + 3.3 v ( 0.3 v) power supply ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? decoupling capacitors mounted on substrate ? all inputs, outputs are lvttl compatible ? serial presence detect with e 2 prom ? uses infineon 256 mbit sdram components in 32m 8 organization and tsopii-54 packages ? gold contact pads, card size: 133.35 mm 31.75 mm 4.00 mm product speed cl t rcd t rp -7.5 pc133 3 3 3 -8 pc100 2 2 2 -8a pc100 3 2 2 ? sdram performance: -7.5 -8 -8a unit pc133 pc100 pc100 f ck clock frequency (max.) 133 100 100 mhz t ac clock access time 5.4 6 6 ns
hys 64/72v32300gu sdram-modules data book 2 3.00 note: all part numbers end with a place code designating the die revision. consult factory for current revision. example: hys 64v32300gu-8-a, indicating rev. a dies are used for sdram components. ordering information type code package descriptions module height hys 64v32300gu-7.5-a hys 64v32300gu-7.5-c pc133-333-520 l-dim-168-33 pc133 32m 64 1 bank sdram module 1.25 hys 72v32300gu-7.5-a hys 72v32300gu-7.5-c pc133-333-520 l-dim-168-33 pc133 32m 72 1 bank ecc-sdram module 1.25 hys 64v32300gu-8-a hys 64v32300gu-8-c pc100-222-620 l-dim-168-33 pc100 32m 64 1 bank sdram module 1.25 hys 72v32300gu-8-a hys 72v32300gu-8-c pc100-222-620 l-dim-168-33 pc100 32m 72 1 bank ecc-sdram module 1.25 hys 64v32300gu-8a-a hys 64v32300gu-8a-c pc100-222-620 l-dim-168-33 pc100 32m 64 1 bank sdram module 1.25 hys 72v32300gu-8a-a hys 72v32300gu-8a-c pc100-222-620 l-dim-168-33 pc100 32m 72 1 bank ecc-sdram module 1.25
hys 64/72v32300gu sdram-modules data book 3 3.00 pin definitions and functions a0 - a12 address inputs clk0 - clk3 clock input ba0, ba1 bank selects dqmb0 - dqmb7 data mask dq0 - dq63 data input/output cs0 - cs3 chip select cb0 - cb7 check bits (x72 organisation only) v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out for presence detect cke0, cke1 clock enable n.c./du no connection address format part number rows columns bank select refresh period interval 32m 64/72 hys64/72v32300gu 13 10 2 8k 64 ms 7.8 m s pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3dq1 45cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 n.c. (cb2) 94 dq39 136 cb6 11 dq8 53 n.c. (cb3) 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52
hys 64/72v32300gu sdram-modules data book 4 3.00 note: pin names in parantheses are for the x72 ecc versions; example: pin 106 = (cb5) 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 n.c. (cb0) 63 cke1 105 n.c. (cb4) 147 n.c. 22 n.c. (cb1) 64 v ss 106 n.c. (cb5) 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 a12 168 v dd pin configuration (contd) pin# symbol pin# symbol pin# symbol pin# symbol
hys 64/72v32300gu sdram-modules data book 5 3.00 block diagram: 32m 64/72 one bank sdram dimm modules spb03970 dq0-dq7 dqm we d0 cs0 we dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm d4 dq0-dq7 dq(15:8) dqmb1 dqm d1 cs dq0-dq7 dq(47:40) dqmb5 dqm d5 dq0-dq7 cb(7:0) dqm cs d8 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs2 cs cs cs d3 d2 dqmb7 dq(63:56) dqmb6 dq(55:48) cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm a0-a11, (a12), ba0, ba1 d0-d7, (d8) cc v ss v c d0-d7, (d8) ras d0-d7, (d8) d0-d7, (d8) cas clock wiring 32 m x 64 32 m x 72 clk0 4 sdram + 3.3 pf 5 sdram termination termination clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 clk3 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp w cs cs we we we we cs we we we we d0-d7, (d8) cke0 d0-d7, (d8) termination termination note: d8 is only used in the x72 ecc version.
hys 64/72v32300gu sdram-modules data book 6 3.00 dc characteristics t a = 0 to 70 c; v ss =0v; v dd , v ddq =3.3v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il C0.5 0.8 v output high voltage ( i out =C4.0ma) v oh 2.4 C v output low voltage ( i out =4.0 ma) v ol C0.4v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) C40 40 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C40 40 m a capacitance t a = 0 to 70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit max. 32m 64 max. 32m 72 input capacitance ( a0 to a11, ba0, ba1, ras , cas , we ) c i1 65 72 pf input capacitance (cs0 - cs3 ) c i2 32 40 pf input capacitance (clk0 - clk3) c icl 38 40 pf input capacitance (cke0, cke1) c i3 65 72 pf input capacitance (dqmb0 - dqmb7) c i4 13 16 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 10 pf input capacitance (scl, sa0-2) c sc 88pf input/output capacitance c sd 88pf
hys 64/72v32300gu sdram-modules data book 7 3.00 notes 1. all values are shown per one sdram component. 2. these parameters depend on the cycle rate. these values are measured at 133 mhz operation frequency for -7.5 and at 100 mhz for -8 and-8a modules. input signals are changed once during t ck , excepts for i cc6 and for stand-by currents when t ck =infinity. 3. these parameters are measured with continuous data stream during read access and all dq toggling. cl = 3 and bl = 4 are assumed and the v ddq current is excluded. operating currents per sdram component 1) t a = 0 to 70 o c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter test condition symbol -7.5 -8/-8a unit note max. operating current t rc = t rcmin. , t ck = t ckmin. outputs open, burst length = 4, cl = 3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access C i cc1 270 210 ma 2) precharge stand-by current in power down mode cs = v ih(min.) , cke v il(max.) t ck =min. i cc2p 22 ma 2) precharge stand-by current in non-power down mode cs = v ih (min.) , cke 3 v ih(min.) t ck =min. i cc2n 25 19 ma 2) no operating current t ck = min., cs = v ih(min.) , active state (max. 4 banks) cke 3 v ih(min.) i cc3n 50 45 ma 2) cke v il(max.) i cc3p 10 10 ma 2) burst operating current t ck =min., read command cycling C i cc4 80 70 ma 2), 3) auto refresh current t ck =min., auto refresh command cycling C i cc5 140 130 ma 2) self refresh current self refresh mode, cke = 0.2 v i cc6 2.5 2.5 ma 2)
hys 64/72v32300gu sdram-modules data book 8 3.00 ac characteristics 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 12 C C 10 10 C C ns ns C system frequency cas latency = 3 cas latency = 2 for hyb64/72v32300gu-7.5-a for hyb64/72v32300gu-7.5-c f ck C C C 133 83 100 C C C 100 100 100 mhz mhz mhz C *) *) clock access time cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 ns ns 2), 3) clock high pulse width t ch 2.5 C 3 C ns 4) clock low pulse width t cl 2.5 C 3 C ns 4) setup and hold parameters input setup time t is 1.5 C 2 C ns 5) input hold time t ih 0.8 C 1 C ns 5) power down mode entry time t sb C1C1clk 6) power down mode exit setup time t pde 1C1Cclk 7) mode register setup time t rsc 2C2Cclk transition time (rise and fall) t t 1C1CnsC common parameters ras to cas delay t rcd 20 C 20 C ns C precharge time t rp 20 C 20 C ns C active command period t ras 45 100k 50 100k ns C cycle time t rc 67.5 C 70 C ns C bank to bank delay time t rrd 15 C 16 C ns C cas to cas delay time (same bank) t ccd 1C1CclkC
hys 64/72v32300gu sdram-modules data book 9 3.00 refresh cycle refresh period (8192 cycles) t ref C64C64msC self refresh exit time t srex 1C1Cclk 8) read cycle data out hold time t oh 3C3Cns 2) data out to low impedance t lz 0C0CnsC data out to high impedance t hz 3738ns 9) dqm data out disable latency t dqz C2C2clkC write cycle data input to precharge (write recovery) t wr 2C2CclkC dqm write mask latency t dqw 0C0CclkC ac characteristics (contd) 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max.
hys 64/72v32300gu sdram-modules data book 10 3.00 ac characteristics 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -8a pc100-322 min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 10 12 C C ns ns C system frequency cas latency = 3 cas latency = 2 f ck C C 100 83 mhz mhz C access time from clock cas latency = 3 cas latency = 2 t ac C C 6 6 ns ns 2), 3) clock high pulse width t ch 3Cns 4) clock low pulse width t cl 3Cns 4) setup and hold times input setup time t is 2Cns 5) input hold time t ih 1Cns 5) power down mode entry time t sb C1clk 6) power down mode exit setup time t pde 1Cclk 7) mode register setup time t rsc 2CclkC transition time t t 0.5 10 ns C common parameters row to column delay time t rcd 20 C ns 5) row precharge time t rp 20 C ns 5) row active time t ras 50 100k ns 5) row cycle time t rc 70 C ns 5) activate (a) to activate (b) command period t rrd 16 C ns 5) cas (a) to cas (b) command period t ccd 1CclkC
hys 64/72v32300gu sdram-modules data book 11 3.00 refresh cycle refresh period (8192 cycles) t ref C64msC self refresh exit time t srex 10 C ns 8) read cycle data out hold time t oh 3Cns 2) data out to low impedance time t lz 0CnsC data out to high impedance time t hz 38ns 9) dqm data out disable latency t dqz C2clkC write cycle data input to precharge (write recovery) t wr 2CclkC dqm write mask latency t dqw 0CclkC ac characteristics (contd) 1), 2) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -8a pc100-322 min. max.
hys 64/72v32300gu sdram-modules data book 12 3.00 notes 1. all ac characteristics are shown for device level. an initial pause of 100 m s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v/ ns edge rate between 0.8 v and 2.0 v. 3. if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns must be added to this parameter. 4. rated at 1.4 v. 5. if t t is longer than 1 ns, a time ( t t - 1) ns must be added to this parameter. 6. whenever the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 7. timing is a asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. 8. self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 9. this is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels. note: *) 256mbyte pc133 modules with place code -c indicating rev. c dies are used as memory components are fully pc100 2-2-2 backwards compatible, where pc133 modules with place code -a operates as pc100 3-2-2 on a 100 mhz memory bus. a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys 64/72v32300gu sdram-modules data book 13 3.00 spd-table for pc133 modules byte# description spd entry value hex 32m 64 -7.5 32m 72 -7.5 0 number of spd bytes 128 80 80 1 total bytes in serial pd 256 08 08 2 memory type sdram 04 04 3 number of row addresses (without bs bits) 13 0d 0d 4 number of column addresses 10 0a 0a 5 number of dimm banks 1 01 01 6 module data width 64/72 40 48 7 module data width (contd) 0 00 00 8 module interface levels lvttl 01 01 9 sdram cycle time at cl = 3 7.5 ns 75 75 10 sdram access time from clock at cl = 3 5.4 ns 54 54 11 dimm config none/ecc 00 02 12 refresh rate/type self-refresh, 7.8 m s82 82 13 sdram width, primary x8 08 08 14 error checking sdram data width n/a/x8 00 08 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 01 16 burst length supported 1, 2, 4 & 8 0f 0f 17 number of sdram banks 4 04 04 18 supported cas latencies cas latency = 2 & 3 06 06 19 cs latencies cs latency = 0 01 01 20 we latencies write latency = 0 01 01 21 sdram dimm module attributes non buffered/non reg. 00 00 22 sdram device attributes: general v dd tol +/C 10% 0e 0e 23 min. clock cycle time at cas latency = 2 for hys64/72v32300gu-7.5-a 12.0 ns c0 c0 min. clock cycle time at cas latency = 2 for hys64/72v32300gu-7.5-c 10.0 ns a0 a0 24 max. data access time from clock for cl = 2 6.0 ns 60 60 25 minimum clock cycle time at cl = 1 not supported ff ff 26 maximum data access time from clock at cl = 1 not supported ff ff 27 minimum row precharge time 20 ns 14 14 28 minimum row active to row active delay t rrd 15 ns 0f 0f 29 minimum ras to cas delay t rcd 20 ns 14 14 30 minimum ras pulse width t ras 45 ns 2d 2d 31 module bank density (per bank) 256 mbyte 40 40 32 sdram input setup time 1.5 ns 15 15
hys 64/72v32300gu sdram-modules data book 14 3.00 33 sdram input hold time 0.8 ns 08 08 34 sdram data input hold time 1.5 ns 15 15 35 sdram data input setup time 0.8 ns 08 08 62-61 superset information (may be used in future) Cffff 62 spd revision revision 1.2 12 12 63 checksum for bytes 0 - 62 for hys64/72v32300gu-7.5-a C5668 checksum for bytes 0 - 62 for hys64/72v32300gu-7.5-c C3648 64-125 manufacturers information (optional) (ff h if not used) Cxxxx 126 frequency specification 64 64 127 100 mhz support details for hys64/72v32300gu-7.5-a for hys64/72v32300gu-7.5-c C ad af ad af 128+ unused storage locations C ff ff spd-table for pc133 modules (contd) byte# description spd entry value hex 32m 64 -7.5 32m 72 -7.5
hys 64/72v32300gu sdram-modules data book 15 3.00 spd-table for pc100 modules byte# description spd entry value hex 32m 64 one bank -8 32m 64 one bank -8a 32m 72 one bank -8 32m 72 one bank -8a 0 number of spd bytes 128 80 80 80 80 1 total bytes in serial pd 256 08 08 08 08 2 memory type sdram 04 04 04 04 3 number of row addresses (without bs bits) 13 0d 0d 0d 0d 4 number of column addresses 10 0a 0a 0a 0a 5 number of dimm banks 1 01 01 01 01 6 module data width 64/72 40 40 48 48 7 module data width (contd) 0 00 00 00 00 8 module interface levels lvttl 01 01 01 01 9 sdram cycle time at cl = 3 10.0ns a0a0a0a0 10 sdram access time from clock at cl = 3 6.0 ns 60 6.0 60 60 11 dimm config none/ecc 00 00 02 02 12 refresh rate/type self-refresh, 7.8 m s 82 82 82 82 13 sdram width, primary x8 08 08 08 08 14 error checking sdram data width n/a/x8 00 00 08 08 15 minimum clock delay for back-to-back random column address t ccd =1clk01010101 16 burst length supported 1, 2, 4 & 8 0f 0f 0f 0f 17 number of sdram banks 4 04 04 04 04 18 supported cas latencies cas latency = 2 &3 06 06 06 06 19 cs latencies cs latency = 0 01 01 01 01 20 we latencies write latency =0 01 01 01 01 21 sdram dimm module attributes non buffered/ non reg. 00 00 00 00 22 sdram device attributes: general v dd tol +/C 10% 0e 0e 0e 0e 23 min. clock cycle time at cas latency = 2 10.0/15.0 ns a0 f0 a0 f0
hys 64/72v32300gu sdram-modules data book 16 3.00 24 max. data access time from clock for cl = 2 6.0/7.0 ns 60 60 60 60 25 minimum clock cycle time at cl = 1 not supported ff ff ff ff 26 maximum data access time from clock at cl = 1 not supported ff ff ff ff 27 minimum row precharge time 20/30 ns 14 14 14 14 28 minimum row active to row active delay t rrd 16/20 ns 10 14 10 14 29 minimum ras to cas delay t rcd 20 ns 14 14 14 14 30 minimum ras pulse width t ras 50/60 ns 32 32 32 32 31 module bank density (per bank) 256mbyte40404040 32 sdram input setup time 2 ns 20 20 20 20 33 sdram input hold time 1 ns 10 10 10 10 34 sdram data input setup time 2ns 20202020 35 sdram data input hold time 1ns 10101010 62-61 superset information (may be used in future) C ffffffff 62 spd revision revision 1.2 12 12 12 12 63 checksum for bytes 0 - 62 C 99 ed ab ff 64-125 manufacturers information C xx xx xx xx 126 frequency specification 100 mhz 64 64 64 64 127 100 mhz support details C af ad af ad 128+ unused storage locations C ff ff ff ff spd-table for pc100 modules byte# description spd entry value hex 32m 64 one bank -8 32m 64 one bank -8a 32m 72 one bank -8 32m 72 one bank -8a
hys 64/72v32300gu sdram-modules data book 17 3.00 package outlines 133,35 1 84 17,78 10 11 40 41 85 127,35 168 124 125 66,68 42,18 x) x) on ecc modules only 31.75 94 95 1,27 + 0.1 - dm168-33.wmf 3 1,27 - + - 0,2 0,15 2,54 min. + - 1 0,05 details of contacts 3 max. 2 l-dim-168-33 sdram dimm module package hys 64/72v32300gu

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